TSMC announced that it would mass produce 2 Nano chips in 2025. What is the backing behind it?

为了保持和加强台积电的技术领先地位，该公司计划继续大力投资研发。对于先进的CMOS逻辑，该公司的3nm和2nm CMOS节点将继续在管道中发展。此外，该公司加强的探索性研发工作主要集中在BEYNON-2nm节点上，以及3D晶体管、新存储器和低R互连等领域，它们正在为建立技术平台提供坚实的基础。

To maintain and strengthen TSMC's technology leadership, the Company plans to continue investing heavily in R&D. For advanced CMOS logic, the Company's 3nm and 2nm CMOS nodes continue to progress in the pipeline. In addition, the Company's reinforced exploratory R&D work is focused on beyond-2nm node and on areas such as 3D transistors, new memory and low-R interconnect, which are on track to establish a solid foundation to feed into technology platforms.

以上段落是摘自台积电官网的未来研发计划。从这个描述可以看出，台积电剑指的是2nm甚至更先进的技术。当接近物理极限时，新工艺研发的难度以及人力和资本的投资也呈指数增长。在这样困难的背景下，台积电的实力是什么？我认为有以下三点：

The above paragraph is the future R & D plan extracted from TSMC's official website. From this description, it can be seen that TSMC sword refers to 2nm or even more advanced technology. When approaching the physical limit, the difficulty of new process R & D and the investment of manpower and capital also increased exponentially. Under such a difficult background, what is the strength of TSMC? I think there are three points as follows:

当前的高级流程节点只是一个商业代码，而不是Gete lenth或half pitch

The current advanced process node is only a commercial code, not Gete lenth or half pitch

如果有人问，芯片技术中的7Nm和5nm意味着什么？然后我相信很多人都能给出答案——晶体管导电沟道的长度或栅极宽度，很多人也知道电流7Nm和5nm只是等效的工艺节点，而不是真正的沟道长度或栅极宽度。

If someone asks, what do 7Nm and 5nm in chip technology mean? Then I believe many people can give the answer - the length of the transistor conductive channel or the gate width, and many people also know that the current 7Nm and 5nm are only equivalent process nodes, not the real channel length or gate width.

如果您进一步问这个问题，当前5nm工艺的实际导电沟道长度或栅极宽度是多少？恐怕很多人回答不了。别担心。IEEE给出的半导体工艺路线图数据相对可靠。我们可以从下图中看到对应于不同时间的流程节点。此表中当前流程节点的英文描述非常有趣。它不使用"技术节点"，而是使用逻辑行业的"节点范围"标签。

If you ask this question further, what is the real conductive channel length or gate width of the current 5nm process? I'm afraid many people can't answer. Don't worry about it. The road map data of semiconductor process given by IEEE is relatively reliable. We can see the process nodes corresponding to different times from the figure below. The English description of the current process node in this table is very interesting. Instead of "technology nodes", it uses logic industry "node range" labeling.

标签可以准确地表示进程命名的当前情况。

A labeling can accurately express the current situation of process naming.

资料来源：IEEE

Source: IEEE

因此，从上表可以看出，5nm工艺节点的栅长为18NM，3nm为16nm，2.1nm为14nm，1.5nm/1.0nm/0.7nm为12NM。在十几纳米尺度上，短沟道效应可以通过各种方法克服，但量子隧穿效应不明显。因此，我完全相信台积电表示，到2030年，它将拥有1nm标签芯片。

Therefore, from the above table, we can see that the gate lenght of 5nm process node is 18NM, 3nm is 16nm, 2.1nm is 14nm, and 1.5nm/1.0nm/0.7nm is 12NM. At the scale of more than ten nanometers, the short channel effect can be overcome by various means, but the quantum tunneling effect is not obvious. Therefore, I fully believe that TSMC says it will have 1nm labeling chips in 2030.

事实上，自从集成电路发明以来，过程节点的定义一直在不断变化。从最初的栅极长度到现在，几乎所有的真实参数，如栅极长度/半节距/鳍节距都被放弃了。尽管目前的流程命名与实际流程有偏差，但很明显，TSMC和三星等商业公司在流程命名方面取得了巨大的商业效益和成功。

In fact, since the invention of integrated circuits, the definition of process nodes has been constantly changing. From the initial gate length to now, almost all kinds of real parameters such as gate length / half pitch / fin pitch have been abandoned. Although the current process naming deviates from the real process, it is obvious that commercial companies such as TSMC and Samsung have obtained great commercial benefits and success in process naming.

这是基础。

This is the foundation one.

不断演变的行业节点定义来源：设备和系统的国际路线图

Evolving Industry Node definitions 来源：INTERNATIONAL ROADMAPFORDEVICES AND SYSTEMS

丰富的资金和资源

Abundant capital and resources

半导体产业链的每个环节都非常紧密，在现阶段，全球半导体巨头也形成了巨大的利益共同体。

Each link of the semiconductor industry chain is very close, and at this stage, the global semiconductor giants have also formed a huge community of interests.

台积电拥有最先进的EUV光刻机

TSMC has the most advanced EUV lithography machine

如果你想把工作做好，你必须先磨快你的工具。作为半导体制造业中最重要的设备，拥有与否决定着一个晶圆厂的工艺极限。

If you want to do a good job, you must first sharpen your tools. As the most important equipment in semiconductor manufacturing, owning or not determines the process limit of a fab.

一台最先进的EUV光刻机价值近10亿美元，对EUV光刻机研发的投资是天文数字。除了ASML，还有两家公司生产平版印刷机——尼康和佳能，但由于投资巨大，两家公司都放弃了研发。

A most advanced EUV lithography machine is worth nearly 1 billion, and the investment in the research and development of EUV lithography machine is astronomical. In addition to ASML, there are two companies manufacturing lithography machines - Nikon and canon, but both gave up research and development because of their high investment.

EUV光的能量和破坏性极高。过程中的所有零件和材料都挑战了人类技术的极限。例如，由于空气分子干扰EUV光，生产过程必须在真空环境中进行。此外，机械作用的误差仅为皮秒（百万分之一秒）。ASML总裁兼首席执行官彼得·温尼克（Peter wennick）表示："如果我们不交出EUV，摩尔定律就会停止。"。因此，五年前，有一笔惊人的交易让ASML声名鹊起——相互竞争的三大巨头，如英特尔、台积电和三星，共同投资了ASML 41亿欧元、8.38亿欧元和5.03亿欧元。

The energy and destructiveness of EUV light are extremely high. All parts and materials in the process challenge the limits of human technology. For example, because air molecules interfere with EUV light, the production process has to be in a vacuum environment. Moreover, the mechanical action is accurate to an error of only picoseconds (millionths of a second). "If we don't hand in the EUV, Moore's law will stop," said Peter wennick, President and CEO of ASML. Therefore, five years ago, there was a startling transaction that made ASML famous - the three giants competing with each other, such as Intel, TSMC and Samsung, jointly invested ASML 4.1 billion, 838 million and 503 million euros.

反过来，台积电可以从ASML订购EUV光刻机，用于新工艺研发和产能扩张。

In turn, TSMC can order EUV lithography machines from ASML for new process R & D and capacity expansion.

台积电拥有最富有的客户

TSMC has the richest customers

但说到每一代台积电的第一项技术，总有一个特殊的客户，苹果。

But when it comes to the first technology of each generation of TSMC, there is always a special customer, apple.

5nm、3nm甚至2nm技术由苹果和台积电联合开发。因此，苹果在台积电先进技术的生产能力中具有不可撼动的地位。它将在一段时间内垄断行业最先进的技术，并吃掉所有的工艺红利。同时，苹果也是台积电最大的客户，去年为台积电贡献了782.8亿元的收入。

5nm, 3nm and even 2nm technologies are jointly developed by apple and TSMC. Therefore, Apple has an unbreakable position in the production capacity of TSMC's advanced technology. It will monopolize the most advanced technology in the industry for a period of time and eat all the process dividends. At the same time, apple is also the largest customer of TSMC, contributing 78.28 billion yuan of revenue to TSMC last year.

这是基础气体二号。

This is base gas two.

2025? 三星也可以！

2025? Samsung can also!

在今年10月举行的2021年三星OEM论坛会议上，三星披露了最新的流程进展和路线图。三星OEM市场战略高级副总裁Moonsoo Kang透露，2gap工艺将在2025年大规模生产。随着FinFET晶体管结构潜力的耗尽，未来将在3nm和2nm中使用GAA晶体管和2.5d/3d堆叠技术，以实现更好的沟道控制和降低功耗。

At the 2021 conference of Samsung OEM forum in October this year, Samsung disclosed the latest process progress and roadmap. Moonsoo Kang, senior vice president of Samsung OEM market strategy, revealed that 2gap process will be mass produced in 2025. As the structural potential of FinFET transistors is exhausted, GAA transistors and 2.5d/3d stacking technology will be used in 3nm and 2nm in the future to achieve better channel control and reduce power consumption.

新技术是三星TSMC的基础。

The new technology is the foundation of Samsung TSMC.

晶体管演变

Transistor evolution

为什么要追求先进技术？

Why pursue advanced technology?

工艺技术的改进可以带来更高的晶体管密度、更强的性能和更低的功耗。

The improvement of process technology can bring higher transistor density, stronger performance and lower power consumption.

我们回到工艺的原始定义，即芯片为7Nm，5nm工艺中的7Nm是指晶体管导电沟道的长度，通常认为是晶体管的栅极宽度。

We return to the original definition of the process, that is, the chip is 7Nm, and 7Nm in the 5nm process refers to the length of the conductive channel of the transistor, which is generally considered to be the gate width of the transistor.

那么，为什么栅极的宽度会影响性能和功耗呢？让我们从性能开始。好的性能意味着在一定的时间内做更多的事情，在处理器中进行更多的操作。我们可以计算一次，当半导体晶体管每次改变0/1时，红色栅极越宽，两个绿色电极越远，它们直接连接一次所需的时间就越长。这就像一个人在10分钟内做25米的往返必须超过50米。因此，栅极越小，晶体管一次状态改变所需的时间越短，单位时间内的工作时间越多，并且一堆晶体管自然可以在单位时间内进行更多操作，因此性能更好。

So why does the width of the gate affect performance and power consumption? Let's start with performance. Good performance means doing more things in a certain time, and more operations in the processor. We can calculate once when the semiconductor transistor changes by 0 / 1 every time, then the wider the Red Gate, the farther the two green electrodes are, and the longer it takes them to connect directly once. This is like a person doing 25m round-trip in 10 minutes must be more than 50m round-trip. Therefore, the smaller the gate, the shorter the time required for one state change of the transistor, the more work times per unit time, and a pile of transistors can naturally do more operations per unit time, so the performance is better.

Link：https://new.qq.com/omn/20211108/20211108A04X1D00.html

update time：2021-11-08 14:58:01